74HC00D Electronic IC Chips Quad 2-input NAND gate

74HC00; 74HCT00
Quad 2-input NAND gate

FEATURES
• Complies with JEDEC standard no. 8-1A
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
• Specified from −40 to +85 °C and −40 to +125 °C.

DESCRIPTION
The 74HC00/74HCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC00/74HCT00 provide the 2-input NAND function.

QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.

Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW).
P_D = C_PD × V_CC² × f_i × N + Σ(C_L × V_CC² × f_o) where:
f_i = input frequency in MHz;
f_o = output frequency in MHz;
C_L = output load capacitance in pF;
V_CC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. For 74HC00 the condition is V_I = GND to V_CC.
For 74HCT00 the condition is V_I = GND to V_CC − 1.5 V.

Fig.1 Pin configuration DIP14, SO14 and (T)SSOP14.


Fig.2 Pin configuration DHVQFN14. Fig.3 Logic diagram (one gate).














Fig.4 Function diagram. Fig.5 IEC logic symbol.

electronic integrated circuit

linear integrated circuits

74HC00D Electronic IC Chips Quad 2-input NAND gate Images